As designs of complex integrated semiconductor devices have evolved, there has been constant demand for greater function, increased performance and decreased power consumption in a single device. In order to meet these demands, designers have found ways to shrink transistor geometries, reduce parasitic effects and leakages, and increase speeds. Each time a specific technology reaches its limits of performance, designers come up with new technologies and design strategies to permit a whole new generation of smaller, denser, more efficient semiconductor devices. This pattern of continual evolution in semiconductor device design has continued essentially unabated for nearly four decades and shows no signs of stopping.
At present, critical dimensions in semiconductor fabrication processes have been reduced into the deep sub-micron range. Downscaling of certain critical dimensions, (e.g., gate length of a MOS transistor), however, has a cost: the degradation of related device characteristics. Often this degradation is significant enough that the advantages obtained by decreasing feature sizes may be offset. By way of example: as the thickness of gate dielectrics has been reduced (now well under 20 angstroms in thickness), one result has been increased gate leakage currents and increased diffusion of dopants from polysilicon gate structures (often referred to as the “poly depletion effect”). Alternatives to doped polysilicon, such as metals and silicides, are now being used in gate structures to mitigate the poly depletion effect and control the leakage current, and thus to ensure electrical performance in highly integrated CMOS devices.
Silicides are alloys of silicon and metals. In modern semiconductor processing, it has become increasingly common to use silicides as conductor materials in silicon device manufacturing. Silicides of titanium (e.g., TiSi2), cobalt (CoSi2), nickel (NiSi2) and various other metals have been employed successfully as conductor materials. When used in this manner, suicides combine the advantages of metals and polysilicon (also known as poly-Si, or just “poly”), exhibiting very low resistivity—significantly lower than poly-Si—and little or no electromigration.
Silicides are formed by means of an anneal (sintering) process known as “silicidation” that results in the formation of a metal-Si alloy (silicide) to act as a conductor or electrode. For example, Ti can be deposited on Si and annealed in an RTA (rapid thermal annealing) process to form TiSi2. The silicide formation process begins at the interface between the Si and the deposited metal and “grows” outward from there. Any unconverted metal can then be removed by selective etching.
A self-aligning variant of the silicidation process, called “salicidation” or “salicide process” (terms formed by merging the letters “S” and “A” for “Self-Aligning” with the words “silicidation” and “silicide”, respectively), is a process in which silicide conductors are formed only in those areas in which deposited metal (which after annealing becomes a metal component of the silicide) is in direct contact with silicon.
A silicide gate is typically formed by salicidation, in which a doped polysilicon gate is covered with a layer of silicide-forming metal (e.g. Co) and then converted to a metal silicide (by silicidation). A silicide gate conductor provides better device performance than a conventional polysilicon gate due to reduced gate dopant depletion, but the best overall performance is achieved only when the gate is fully and uniformly silicided. While many processes claim to produce “fully-silicided” gate conductors, their reliance on the “gradient” nature of silicide formation tends to produce non-uniform silicide composition in the gate (due to non-uniform conversion of gate polysilicon to silicide). It is generally difficult to convert polysilicon in the gate uniformly and completely into silicide because of long diffusion path and compressive stress due to volume expansion associated with the silicidation process. When polysilicon is not fully and uniformly converted to silicide, device performance is degraded and device-to-device parameter variation is increased due to device-to-device variations in the gate silicide composition.
Another issue (generally unrelated to gate silicidation) produced by continued downscaling of critical dimensions into the deep sub-micron range is that conventional lithographic patterning techniques are pushed beyond their minimum feature size limitations. It has become necessary to consider techniques for sub-lithographic feature patterning on semiconductor wafers (i.e., patterning feature sizes smaller than can be accomplished using convention lithographic techniques).
The current state of the art (and future CMOS technology) requires sub-50 nm metal conductors for connecting the CMOS devices, such as field effect transistors (FETs), to the back-end-of-line (BEOL) wiring. However, the currently available 0.93 numerical aperture (NA) lithographic tools can only resolve lithographic patterns with openings of 100 nm in diameter or greater. Future generations of 1.2 NA lithographic tools are expected to produce lithographic patterns with openings as small as 70 nm to 80 nm in diameter, but not nearly small enough to produce the desired 50 nm diameter. Without a means of producing the smaller, desired opening, maximum potential circuit density cannot be achieved. This is only one example of how conventional lithographic tools are at or beyond their limits in trying to produce certain desired semiconductor features, pointing to a need for sub-lithographic feature patterning.
Due to the challenges involved in fabricating nanostructures (nanometer-scale structures), new techniques and materials are constantly being sought to make nanofabrication (fabrication of nanostructures) easier, cheaper and more versatile. Thin films of materials called block copolymers show tremendous potential in this regard because they self-assemble into ordered, chemically distinct (i.e., micro-phase separated) domains with dimensions in the range of 10 to 40 nm. Block copolymer films can be used as templates (i.e., resists) for building nanostructures in semiconductor, optical and magnetic media materials, with sub-lithographic line-widths, margins and tolerances, and line-edge characteristics that are dictated by thermodynamics rather than standard resist processing.
The phenomenon of self-assembly is not unknown in nature. Some easily recognizable examples of self-assembly range from snowflakes to seashells to sand dunes, all of which form some type of regular or ordered patterns in response to specific external conditions. Self-assembling block copolymers behave in much the same way, but producing repeating patterns at nanometer scale dimensions.
Block copolymers are made up of blocks of different polymerized monomers. For example, PS-b-PMMA is short for polystyrene-b-poly(methyl methacrylate) and is made by first polymerizing styrene, and then subsequently polymerizing MMA. This polymer is a “diblock copolymer” because it contains two different chemical blocks. Triblocks, tetrablocks, pentablocks, etc., can also be made. Diblock copolymers are made using “living polymerization” techniques, such as atom transfer free radical polymerization (ATRP), reversible addition fragmentation chain transfer (RAFT), living cationic or living anionic polymerizations. Block copolymers are especially interesting in the present context because of their ability to “microphase separate” to form periodic nanostructures under the right thermodynamic conditions.
FIG. 1A is a plan view of a prior art structure 100 including a regular, patterned planar array of nanometer-scale vertical columns 104 of a first polymer formed within and surrounded on all sides by a planar layer of a second polymer 102. This regular patterned array is formed by self-assembly of a diblock copolymer comprising a mixture of the first and second copolymers, in this case polystyrene (columns 104) and PMMA (surrounding field 102).
FIG. 1B is a cross-sectional view of the prior art structure 100 described above with respect to FIG. 1A. The regular, patterned array of structures comprising nanometer-scale vertical polystyrene columns 104 and the surrounding planar field of PMMA 102 are formed on a surface of a substrate material 106. This substrate 106 can be a semiconductor wafer in process, an optical material or a magnetic media material.
Despite the usefulness of block copolymers for forming nanostructures on semiconductor wafers, they have not been shown to be particularly useful for present for patterning CMOS devices. Generally speaking, CMOS technology requires precise placement and registration of individual structural units in order to successfully form metal lines and vias in the wiring layers. The large, ordered arrays of nanometer-scale structures formed by self-assembling block copolymers may be regular, but their spatial frequency is dependent upon copolymer composition and for all practical purposes, their spatial “phase” is not predictable. As a result, the patterns produced by these self-assembling block copolymers lack the precise and predictable alignment and registration required to produce structures useful for lines and vias in CMOS technology.